Fault-tolerant clock systems using redundant clock sources have been available for providing timing signals in the face of the failure of one or more of the individual clock sources therein. Certain systems, such as shown in U.S. Pat. No. 3,479,603 issued on Nov. 18, 1969 to R. L. Overstreet, Jr., require relatively complex self-testing circuitry while other systems, such as shown in U.S. Pat. No. 3,278,852 issued on Oct. 11, 1966 to W. C. Mann, rely on a majority decision among redundant sources which, as arranged therein, could cause erroneous output pulses to be formed. Still other systems utilize the approach of detecting, isolating and correcting faults as they occur, a design which requires a determination of all failure modes prior to design thereby producing a complex and expensive system.
One reasonably successful system has also been described in U.S. Pat. No. 3,900,741 issued on Aug. 19, 1975 to Fletcher et al. Such system requires a total of (3r+1) clock elements to provide tolerance for r faults, where r is any positive integer.
It is desirable to reduce the number of redundant clock sources required for tolerating the same number of clock failures, thereby reducing the cost and complexity of the system, while still retaining the precision of control that is desired in applications in which the systems are used. Moreover, such systems should provide for convenient methods for compensating for circuit phase delays so that relatively high clock frequencies can be used.
Further, it is desirable that the jitter, which is present in most systems due to phase noise, be capable of being minimized.
The system discussed in the above Fletcher et al patent suffers from the above problems and, moreover, utilizes fixed delay elements therein so that a high degree of frequency control precision is difficult to achieve.